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1 Reply Latest reply: Jan 11, 2013 11:51 AM by adiadmin RSS

请教关于ADF7020的发送与接收数据的问题

初学者
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最近参考官方的原理图,设计了几块ADF7020的收发电路.
但发现把芯片配置成发送模式后,给DATA I/O脚送数据.
在频谱仪上设置的某个频段什么都看不到.
有点怀疑是VCO没有工作起来,请问如何调试PLL和VCO有没正常工作呢?

 

对于接收模式来说,REG4中的DEMOD
MODE 2 (FREE RUNNING)和MODE 3 (LOCK
THRESHOLD)有什么区别呢?
如果把芯片配置成以上两种模式的其中一种,接收数据正确的情况下,INT/LOCK会有电平的改变吗?或者怎样判断芯片开始收到数据呢?

 

问题有点多.非常感谢各位~

  • Re: 请教关于ADF7020的发送与接收数据的问题
    adiadmin 普通专家
    Currently Being Moderated

    您好!

     

    对于PLL是否锁定,您可以设置MUXOUT输出为Digital Lock Dectect模式。如果锁定,MUXOUT输出为高电平。
    对于检测接收数据问题,数据手册中描述如下:
    The ADF7020 also supports automatic detection of the sync or ID fields. To activate this mode, the sync (or ID) word must be preprogrammed into the ADF7020. In receive mode, this preprogrammed word is compared to the received bit stream and, when a valid match is identified, the external pin INT/LOCK is asserted by the ADF7020.
    This feature can be used to alert the microprocessor that a valid channel has been detected. It relaxes the computational require-ments of the microprocessor and reduces the overall power consumption. The INT/LOCK is automatically deasserted again after nine data clock cycles.
    The automatic sync/ID word detection feature is enabled by selecting Demodulator Mode 2 or Demodulator Mode 3 in the demodulator setup register. Do this by setting Bits R4_DB[25:23] = 010 or 011. Bits R5_DB[4:5] are used to set the length of the sync/ID word, which can be 12, 16, 20, or 24 bits long. The transmitter must transmit the MSB of the sync byte first and the LSB last to ensure proper alignment in the receiver sync byte detection hardware.
    For systems using forward error correction (FEC), an error tolerance parameter can also be programmed that accepts a valid match when up to three bits of the word are incorrect. The error tolerance value is assigned in Bits R5_DB[6:7].
    希望对您有所帮助。

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