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1 Reply Latest reply: Jan 11, 2013 12:00 PM by adiadmin RSS

求助:多片AD9739的同步如何实现?

初学者
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用FPGA控制两片AD9739(以下简称A和B),其中A的SYNC_OUT接到了B的SYNC_IN,而A的SYNC_IN和B的SYNC_OUT接到了FPGA中。
现在配置0x10寄存器,采用无同步模式,两片可以分别工作,但灌入相同信号,每次上电二者无固定相位关系
而配置0x10寄存器让A做sync
master,B做sync
slave,始终无法同步上,而且A的输出不正常。

 

请问应当如何正确配置寄存器以及给相应的同步SYNC_xx信号,才能让二者同步工作起来,每次上电以后两路DA相位固定?
(注:除DACCLK以外,A和B的其他时钟和数据管脚都接到FPGA上,每片的DCI和DATA的时钟由各自的DCO进入FPGA分频产生)

  • Re: 求助:多片AD9739的同步如何实现?
    adiadmin 普通专家
    Currently Being Moderated

    Table II. Recommeded SPI Initialization with SYNCH Controller Enabled

     

     

    StepsAddress (Hex)Write ValueComments
    10x000x004-wire SPI mode with MSB 1st
    20x000x20Software Reset to Default SPI Values*
    30x000x00Clear Reset Bit
    40x220x0FSet common-mode voltage of CLKP and CLKN inputs
    50x230x0F
    60x240x30Configure MU Controller
    70x250x80
    80x270x46
    90x280x6C
    100x290xCB
    110x260x02
    120x260x03Enable MU Controller Search and Track Mode
    13

     

     

    WAIT for 160K * 1/FDATA Cycles
    140x2A

     

    Readback register 0x2A and confirm it is equal to 0x01 to ensure DLL loop is locked. If not, proceed to STEP 10 and repeat. Limit to 3 attempts before breaking out of loop and reporting “MU lock failure”.
    150x150x42Configure SYNC Controller
    160x100x00Disable Sync Controller before Enable
    170x100x70 or
    0x50
    Enable SYNC Controller :
    0x70 (Master Mode)
    0x50 (Slave Mode)
    18

     

     

    WAIT for 160K * 1/FDATA for DLL to lock
    19

     

     

    Readback Register 0x21 to confirm proper operation:
    =0x90 (Master Mode)
    =0x00 (Slave Mode)
    If not, proceed to Step 15 and repeat. Limit to 3 attempts before breaking out of loop and reporting “SYNC lock failure”
    20

     

     

    Readback Register 0x0D and confirm bit[5:4]=”10”
    If not, proceed to Step 15 and repeat. Limit to 3 attempts before breaking out of loop and reporting “SYNC lock failure”.
    210x130x72Set FINE_DEL_SKW to 2
    220x100x70 or
    0x50
    Disable DATA Rx Controller before Enable:
    0x70 (Master Mode)
    0x50 (Slave Mode)
    230x100x73 or
    0x53
    Enable DATA Rx Controller for Search+Track Mode
    24

     

     

    -WAIT for 135K * 1/FDATA Cycles with SYNC Controller OFF
    -WAIT for 555K * 1/FDATA Cycles with SYNC Controller ON
    240x21

     

    Readback register 0x21 to confirm proper operation:
    =0x99 (Master Mode)
    =0x09 (Slave Mode)
    If not, proceed to Step 21 and repeat. Limit to 3 attempts before breaking out of loop and reporting “Rx Data lock failure”.
    25

     

     

    Optional: Modify default TxDAC mode and IOUTFS settings shown in Table III

     

     

     

    Table III. Additional Configuration Registers for TxDAC that can be modified by user

     

    SPI RegisterDefault ValueComments
    0x060x00TxDAC’s IOUTFS=20 mA
    0x070x02
    0x080x00TxDAC operates in NORMAL MODE

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