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AD9361 BBPLL锁定的问题

SongZ 在 2015-7-27 詢問的問題
最後回覆由SongZ於2015-7-28提供

AD9361的配置如下:

 

SPIWrite3DF,01// Required for proper operation
SPIWrite2A6,0E// Enable Master Bias
SPIWrite2A8,0E// Set Bandgap Trim
SPIWrite2AB,07// Set RF PLL reflclk scale to REFCLK * 2
SPIWrite2AC,FF// Set RF PLL reflclk scale to REFCLK * 2
SPIWrite009,17// Enable Clocks
WAIT20// waits 20 ms

 

 

//************************************************************

// Set BBPLL Frequency: 983.040000

//************************************************************

SPIWrite045,00// Set BBPLL reflclk scale to REFCLK /1
SPIWrite046,03// Set BBPLL Loop Filter Charge Pump current
SPIWrite048,E8// Set BBPLL Loop Filter C1, R1
SPIWrite049,5B// Set BBPLL Loop Filter R2, C2, C1
SPIWrite04A,35// Set BBPLL Loop Filter C3,R2
SPIWrite04B,E0// Allow calibration to occur and set cal count to 1024 for max accuracy
SPIWrite04E,10// Set calibration clock to REFCLK/4 for more accuracy
SPIWrite043,29// BBPLL Freq Word (Fractional[7:0])
SPIWrite042,5C// BBPLL Freq Word (Fractional[15:8])
SPIWrite041,12// BBPLL Freq Word (Fractional[23:16])
SPIWrite044,18// BBPLL Freq Word (Integer[7:0])
SPIWrite03F,05// Start BBPLL Calibration
SPIWrite03F,01// Clear BBPLL start calibration bit
SPIWrite04C,86// Increase BBPLL KV and phase margin
SPIWrite04D,01// Increase BBPLL KV and phase margin
SPIWrite04D,05// Increase BBPLL KV and phase margin
WAIT_CALDONEBBPLL,2000// Wait for BBPLL to lock, Timeout 2sec, Max BBPLL VCO Cal Time: 345.600 us
SPIRead05E// Check BBPLL locked status  (0x05E[7]==1 is locked)

 

读到0x5E的值一直是0xCA、0x02、0三个值循环跳变,这是不是表示BBPLL没有锁定啊,示波器可以采到DATA_CLK为6.83MHz

結果