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AD9363信号输出问题

kenny.qin.2015 在 2015-11-10 詢問的問題
最後回覆由oceancjc_adi於2015-12-29提供

自己画的电路板,使用的AD9363+ep4ce40+ARM。 运行的NO-OS的程序在ARM Linux下,运行结果如下。

# ./ad9361

spi mode: 1

bits per word: 8

max speed: 0 Hz (0 KHz)

gpio_set_value AD9361_RESET->DATA 0

gpio_set_value AD9361_RESET->DATA 1

ad9361_reset: by GPIO

ad9361_rfpll_recalc_rate: Parent Rate 50000000 Hz

ad9361_rfpll_recalc_rate: Parent Rate 50000000 Hz

ad9361_setup

ad9361_set_dcxo_tune : coarse 8 fine 5920

ad9361_set_trx_clock_chain

ad9361_set_trx_clock_chain: 1280000000 80000000 40000000 20000000 10000000 10000000

ad9361_set_trx_clock_chain: 1280000000 80000000 40000000 20000000 10000000 10000000

ad9361_bbpll_set_rate: Rate 1280000000 Hz Parent Rate 50000000 Hz

Reg 0x4A val 0x35

Reg 0x49 val 0x5B

Reg 0x48 val 0xE8

ad9361_rfpll_recalc_rate: Parent Rate 50000000 Hz

ad9361_rfpll_recalc_rate: Parent Rate 50000000 Hz

ad9361_clk_factor_set_rate: Rate 80000000 Hz Parent Rate 1280000000 Hz

ad9361_rfpll_recalc_rate: Parent Rate 50000000 Hz

ad9361_rfpll_recalc_rate: Parent Rate 50000000 Hz

ad9361_clk_factor_set_rate: Rate 10000000 Hz Parent Rate 10000000 Hz

ad9361_rfpll_recalc_rate: Parent Rate 50000000 Hz

ad9361_rfpll_recalc_rate: Parent Rate 50000000 Hz

ad9361_clk_factor_set_rate: Rate 10000000 Hz Parent Rate 10000000 Hz

ad9361_rfpll_recalc_rate: Parent Rate 50000000 Hz

ad9361_rfpll_recalc_rate: Parent Rate 50000000 Hz

ad9361_rssi_setup

ad9361_auxadc_setup

ad9361_rf_port_setup : INPUT_SELECT 0x3

ad9361_pp_port_setup

ad9361_auxdac_setup

ad9361_auxdac_set DAC1 = 0 mV

ad9361_auxdac_set DAC2 = 0 mV

ad9361_auxadc_setup

ad9361_ctrl_outs_setup

ad9361_gpo_setup

ad9361_set_ref_clk_cycles : ref_clk_hz 50000000

ad9361_txrx_synth_cp_calib : ref_clk_hz 50000000 : is_tx 0

ad9361_txrx_synth_cp_calib : ref_clk_hz 50000000 : is_tx 1

ad9361_rfpll_set_rate: Rate 400000000 Hz Parent Rate 50000000 Hz

ad9361_fastlock_prepare: RX Profile 0: Un-Prepare

ad9361_rfpll_vco_init : vco_freq 6400000000 : ref_clk 50000000 : range 1

ad9361_rfpll_vco_init : freq 6373 MHz : index 44

Reg 0x235 val 0x0

Reg 0x234 val 0x0

Reg 0x233 val 0x0

Reg 0x232 val 0x0

Reg 0x231 val 0x80

ad9361_load_gt: frequency 800000000

ad9361_load_gt: frequency 800000000 (band 0)

ad9361_rfpll_recalc_rate: Parent Rate 50000000 Hz

ad9361_rfpll_recalc_rate: Parent Rate 50000000 Hz

ad9361_rfpll_recalc_rate: Parent Rate 50000000 Hz

ad9361_rfpll_set_rate: Rate 400000000 Hz Parent Rate 50000000 Hz

ad9361_fastlock_prepare: TX Profile 0: Un-Prepare

ad9361_rfpll_vco_init : vco_freq 6400000000 : ref_clk 50000000 : range 1

ad9361_rfpll_vco_init : freq 6373 MHz : index 44

Reg 0x275 val 0x0

Reg 0x274 val 0x0

Reg 0x273 val 0x0

Reg 0x272 val 0x0

Reg 0x271 val 0x80

ad9361_rfpll_recalc_rate: Parent Rate 50000000 Hz

ad9361_rfpll_recalc_rate: Parent Rate 50000000 Hz

ad9361_rfpll_recalc_rate: Parent Rate 50000000 Hz

ad9361_load_mixer_gm_subtable

ad9361_gc_setup

ad9361_rx_bb_analog_filter_calib : rx_bb_bw 5000000 bbpll_freq 1280000000

ad9361_run_calibration: CAL Mask 0x80

ad9361_tx_bb_analog_filter_calib : tx_bb_bw 5000000 bbpll_freq 1280000000

ad9361_run_calibration: CAL Mask 0x40

ad9361_rx_tia_calib : bb_bw_Hz 5000000

ad9361_tx_bb_second_filter_calib : tx_bb_bw 5000000

ad9361_rx_adc_setup : BBBW 4802955 : ADCfreq 80000000

c3_msb 0x0 : c3_lsb 0x71 : r2346 0x1 :

invrc_tconst_1e6 981907, sqrt_inv_rc_tconst_1e3 990

scaled_adc_clk_1e6 125000, inv_scaled_adc_clk_1e3 8000

tmp_1e3 1020, sqrt_term_1e3 353, min_sqrt_term_1e3 707

ad9361_bb_dc_offset_calib

ad9361_run_calibration: CAL Mask 0x1

ad9361_rfpll_recalc_rate: Parent Rate 50000000 Hz

ad9361_rf_dc_offset_calib : rx_freq 800000000

ad9361_run_calibration: CAL Mask 0x2

ad9361_tx_quad_calib : bw_tx 5000000 clkrf 10000000 clktf 10000000

Tx NCO frequency: 1250000 (BW/4: 1250000) txnco_word 3

ad9361_run_calibration: CAL Mask 0x10

LO leakage: 0 Quadrature Calibration: 0 : rx_phase 21

ad9361_tx_quad_phase_search

ad9361_run_calibration: CAL Mask 0x10

ad9361_run_calibration: CAL Mask 0x10

ad9361_run_calibration: CAL Mask 0x10

ad9361_run_calibration: CAL Mask 0x10

ad9361_run_calibration: CAL Mask 0x10

ad9361_run_calibration: CAL Mask 0x10

ad9361_run_calibration: CAL Mask 0x10

ad9361_run_calibration: CAL Mask 0x10

ad9361_run_calibration: CAL Mask 0x10

ad9361_run_calibration: CAL Mask 0x10

ad9361_run_calibration: CAL Mask 0x10

ad9361_run_calibration: CAL Mask 0x10

ad9361_run_calibration: CAL Mask 0x10

ad9361_run_calibration: CAL Mask 0x10

ad9361_run_calibration: CAL Mask 0x10

ad9361_run_calibration: CAL Mask 0x10

ad9361_run_calibration: CAL Mask 0x10

ad9361_run_calibration: CAL Mask 0x10

ad9361_run_calibration: CAL Mask 0x10

ad9361_run_calibration: CAL Mask 0x10

ad9361_run_calibration: CAL Mask 0x10

ad9361_run_calibration: CAL Mask 0x10

ad9361_run_calibration: CAL Mask 0x10

ad9361_run_calibration: CAL Mask 0x10

ad9361_run_calibration: CAL Mask 0x10

ad9361_run_calibration: CAL Mask 0x10

ad9361_run_calibration: CAL Mask 0x10

ad9361_run_calibration: CAL Mask 0x10

ad9361_run_calibration: CAL Mask 0x10

ad9361_run_calibration: CAL Mask 0x10

ad9361_run_calibration: CAL Mask 0x10

ad9361_run_calibration: CAL Mask 0x10

############o###############################o################### RX_NCO_PHASE_OFFSET(12, 0xC)

ad9361_run_calibration: CAL Mask 0x10

ad9361_tracking_control : bbdc_track=1, rfdc_track=1, rxquad_track=1

ad9361_pp_port_setup

ad9361_set_tx_atten : attenuation 0 mdB tx1=1 tx2=1

Reg 0x74 val 0x0

Reg 0x73 val 0x0

Reg 0x76 val 0x0

Reg 0x75 val 0x0

ad9361_rssi_setup

ad9361_txmon_setup

Device is in 5 state, moving to a

ad9361_init : AD9361 Rev 2 successfully initialized

ad9361_load_fir_filter_coef: TAPS 64, gain -6, dest 3

ad9361_load_fir_filter_coef: TAPS 64, gain 0, dest 131

sigal test of 1/4 clk, put any char get chirp sigal

 

Available commands:

help?  - Displays all available commands.

register?  - Gets the specified register value.

tx_lo_freq?  - Gets current TX LO frequency [MHz].

tx_lo_freq=  - Sets the TX LO frequency [MHz].

tx_samp_freq?  - Gets current TX sampling frequency [Hz].

tx_samp_freq=  - Sets the TX sampling frequency [Hz].

tx_rf_bandwidth?  - Gets current TX RF bandwidth [Hz].

tx_rf_bandwidth=  - Sets the TX RF bandwidth [Hz].

tx1_attenuation?  - Gets current TX1 attenuation [mdB].

tx1_attenuation=  - Sets the TX1 attenuation [mdB].

tx2_attenuation?  - Gets current TX2 attenuation [mdB].

tx2_attenuation=  - Sets the TX2 attenuation [mdB].

tx_fir_en?  - Gets current TX FIR state.

tx_fir_en=  - Sets the TX FIR state.

rx_lo_freq?  - Gets current RX LO frequency [MHz].

rx_lo_freq=  - Sets the RX LO frequency [MHz].

rx_samp_freq?  - Gets current RX sampling frequency [Hz].

rx_samp_freq=  - Sets the RX sampling frequency [Hz].

rx_rf_bandwidth?  - Gets current RX RF bandwidth [Hz].

rx_rf_bandwidth=  - Sets the RX RF bandwidth [Hz].

rx1_gc_mode?  - Gets current RX1 GC mode.

rx1_gc_mode=  - Sets the RX1 GC mode.

rx2_gc_mode?  - Gets current RX2 GC mode.

rx2_gc_mode=  - Sets the RX2 GC mode.

rx1_rf_gain?  - Gets current RX1 RF gain.

rx1_rf_gain=  - Sets the RX1 RF gain.

rx2_rf_gain?  - Gets current RX2 RF gain.

rx2_rf_gain=  - Sets the RX2 RF gain.

rx_fir_en?  - Gets current RX FIR state.

rx_fir_en=  - Sets the RX FIR state.

 

 

程序里添加了一段初始化fpga内ram的代码,如下:

void init_ram()

{

    int data_i1[8] = {1023, 723, 0, -724, -1024, -724, 0, 723, };

    int data_q1[8] = {0, 723, 1023, 723, 0, -724, -1024, -724, };

    const int RAM_SIZE1 = 8;

    int data_i[4] = {1023, 0, -1024, 0, };

    int data_q[4] = {0, 1023, 0, -1024, };

    const int RAM_SIZE = 4;    

 

    int index = RAM_SIZE - 1;

    ram_write(RAM_I_BASE, data_i, RAM_SIZE);

    ram_write(RAM_Q_BASE, data_q, RAM_SIZE);

    ram_write(COUNTER_BASE, &index, 1);

 

    printf("sigal test of 1/4 clk, put any char get chirp sigal\n");

    getchar();

 

    index = RAM_SIZE1 - 1;

    ram_write(RAM_I_BASE, data_i1, RAM_SIZE1);

    ram_write(RAM_Q_BASE, data_q1, RAM_SIZE1);

    ram_write(COUNTER_BASE, &index, 1);

}

 

fpga内接口用的axi_ad9361_dev_if。配置的单口输入输出。下面第一个图为四个点时的输出,第二个图为8个点时的输出。本振配置的800M。晶振是接的50M。

IMG_20151110_103551.jpg

IMG_20151110_103612.jpg

 

给的点数越多,出来的谐波越多。不知道如何继续调试了,希望得到大家的帮助,谢谢!@

結果