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AD9361 Rx/Tx PLL无法锁定,寄存器配置是否有问题?

maninuo 在 2015-11-17 詢問的問題
最後回覆由oceancjc_adi於2016-3-24提供

使用zedboard + AD-FMCOMMS3调试AD9361,使用Linux工具可以操作AD9361(说明AD9361载板功能正常),但自己写的控制程序却无法完成Rx/Tx PLL的锁定。采用的时钟为AD-FMCOMMS3上的40MHz crystal(BBPLL设置为800MHz,Rx/Tx PLL为2400MHz,VCO为9600MHz),寄存器的配置值及配置顺序均按照参考手册,SPI接口读写正确,BBPLL已锁定,但Rx/Tx PLL一直无法锁定,且寄存器Cal Status (0x244/0x284)的VCO Cal Busy位一直为高。以下是我的具体配置信息,请问配置是否存在问题,另PLL的配置需要关注哪些细节,与哪些寄存器设置有关?

 

// Profile: LTE 20 MHz

// REFCLK_IN: 40.000 MHz 板载DCXO

 

RESET_FPGA

RESET_DUT

 

BlockWrite 2,6 // Set ADI FPGA SPI to 20Mhz

ReadPartNumber          //chip product ID

SPIWrite 3DF,01 // Required for proper operation

SPIWrite 000,00 // SPI Port Config

SPIWrite 2A6,0E // Enable Master Bias

SPIWrite 2A8,0E // Set Bandgap Trim

//REFCLK_Scale 40.0000,1,1 // Sets local variables in script engine, user can ignore

SPIWrite 2AB,06 // Set RF PLL reflclk scale to REFCLK /1

SPIWrite 2AC,73 // Set RF PLL reflclk scale to REFCLK /1

SPIWrite 009,07 // Enable Clocks,external crystal with the DCXO.

WAIT 20 // waits 20 ms

 

 

//************************************************************

// Set BBPLL Frequency: 800.000000MHz

//************************************************************

SPIWrite 045,00 // Set BBPLL reflclk scale to REFCLK /1

SPIWrite 046,03 // Set BBPLL Loop Filter Charge Pump current

SPIWrite 048,E8 // Set BBPLL Loop Filter C1, R1

SPIWrite 049,5B // Set BBPLL Loop Filter R2, C2, C1

SPIWrite 04A,35 // Set BBPLL Loop Filter C3,R2

SPIWrite 04B,E0 // Allow calibration to occur and set cal count to 1024 for max accuracy

SPIWrite 04E,10 // Set calibration clock to REFCLK/4 for more accuracy

SPIWrite 043,00 // BBPLL Freq Word (Fractional[7:0])

SPIWrite 042,00 // BBPLL Freq Word (Fractional[15:8])

SPIWrite 041,00 // BBPLL Freq Word (Fractional[23:16])

SPIWrite 044,14 // BBPLL Freq Word (Integer[7:0])

SPIWrite 03F,05 // Start BBPLL Calibration

SPIWrite 03F,01 // Clear BBPLL start calibration bit

SPIWrite 04C,86 // Increase BBPLL KV and phase margin

SPIWrite 04D,01 // Increase BBPLL KV and phase margin

SPIWrite 04D,05 // Increase BBPLL KV and phase margin

WAIT_CALDONE BBPLL,2000 // Wait for BBPLL to lock, Timeout 2sec, Max BBPLL VCO Cal Time: 225.000 us (Done when 0x05E[7]==1)

 

 

SPIRead 05E // Check BBPLL locked status  (0x05E[7]==1 is locked)

 

 

SPIWrite 002,CE // Setup Tx Digital Filters/ Channels

SPIWrite 003,DE // Setup Rx Digital Filters/ Channels

SPIWrite 004,03 // Select Rx input pin(A,B,C)/ Tx out pin (A,B)

SPIWrite 00A,09 // Set BBPLL post divide rate

 

 

 

 

//************************************************************

// Program Tx FIR: C:\Program Files (x86)\Analog Devices\AD9361

// Evaluation Software v2.1.4 (64-bit)\DigitalFilters\LTE20_MHz.ftr

//************************************************************

//此处按照参考手册上的配置值来配置

 

 

//************************************************************

// Program Rx FIR: C:\Program Files (x86)\Analog Devices\AD9361

// Evaluation Software v2.1.4 (64-bit)\DigitalFilters\LTE20_MHz.ftr

//************************************************************

//此处按照参考手册上的配置值来配置

 

 

//************************************************************

// Setup the Parallel Port (Digital Data Interface)

//************************************************************

SPIWrite 010,C8 // I/O Config.  Tx Swap IQ; Rx Swap IQ; Tx CH Swap, Rx CH Swap; Rx

Frame Mode; 2R2T bit; Invert data bus; Invert DATA_CLK

SPIWrite 011,00 // I/O Config.  Alt Word Order; -Rx1; -Rx2; -Tx1; -Tx2; Invert Rx Frame; Delay Rx Data

SPIWrite 012,02 // I/O Config.  Rx=2*Tx; Swap Ports; SDR; LVDS; Half Duplex; Single Port; Full Port; Swap Bits

SPIWrite 006,0F // PPORT Rx Delay (adjusts Tco Dataclk->Data)

SPIWrite 007,00 // PPORT TX Delay (adjusts setup/hold FBCLK->Data)

SPIWrite 03c,26 // LVDS port config

SPIWrite 03d,ff //

SPIWrite 03e,0f //

 

 

//************************************************************

// Setup AuxDAC

//************************************************************

SPIWrite 018,00 // AuxDAC1 Word[9:2]

SPIWrite 019,00 // AuxDAC2 Word[9:2]

SPIWrite 01A,00 // AuxDAC1 Config and Word[1:0]

SPIWrite 01B,00 // AuxDAC2 Config and Word[1:0]

SPIWrite 023,FF // AuxDAC Manaul/Auto Control

SPIWrite 026,00 // AuxDAC Manual Select Bit/GPO Manual Select

SPIWrite 030,00 // AuxDAC1 Rx Delay

SPIWrite 031,00 // AuxDAC1 Tx Delay

SPIWrite 032,00 // AuxDAC2 Rx Delay

SPIWrite 033,00 // AuxDAC2 Tx Delay

 

 

//************************************************************

// Setup AuxADC

//************************************************************

SPIWrite 00B,00 // Temp Sensor Setup (Offset)

SPIWrite 00C,00 // Temp Sensor Setup (Temp Window)

SPIWrite 00D,03 // Temp Sensor Setup (Periodic Measure)

SPIWrite 00F,04 // Temp Sensor Setup (Decimation)

SPIWrite 01C,10 // AuxADC Setup (Clock Div)

SPIWrite 01D,01 // AuxADC Setup (Decimation/Enable)

 

 

//************************************************************

// Setup Control Outs

//************************************************************

SPIWrite 035,00 // Ctrl Out index

SPIWrite 036,FF // Ctrl Out [7:0] output enable

 

 

//************************************************************

// Setup GPO

//************************************************************

SPIWrite 03A,3C // Set number of REFCLK cycles for 1us delay timer

SPIWrite 020,00 // GPO Auto Enable Setup in RX and TX

SPIWrite 027,03 // GPO Manual and GPO auto value in ALERT

SPIWrite 028,00 // GPO_0 RX Delay

SPIWrite 029,00 // GPO_1 RX Delay

SPIWrite 02A,00 // GPO_2 RX Delay

SPIWrite 02B,00 // GPO_3 RX Delay

SPIWrite 02C,00 // GPO_0 TX Delay

SPIWrite 02D,00 // GPO_1 TX Delay

SPIWrite 02E,00 // GPO_2 TX Delay

SPIWrite 02F,00 // GPO_3 TX Delay

 

 

//************************************************************

// Setup RF PLL non-frequency-dependent registers

//************************************************************

SPIWrite 261,00 // Set Rx LO Power mode

SPIWrite 2A1,00 // Set Tx LO Power mode

SPIWrite 248,0B // Enable Rx VCO LDO

SPIWrite 288,0B // Enable Tx VCO LDO

SPIWrite 246,02 // Set VCO Power down TCF bits

SPIWrite 286,02 // Set VCO Power down TCF bits

SPIWrite 249,8E // Set VCO cal length

SPIWrite 289,8E // Set VCO cal length

SPIWrite 23B,80 // Enable Rx VCO cal

SPIWrite 27B,80 // Enable Tx VCO cal

SPIWrite 243,0D // Set Rx prescaler bias

SPIWrite 283,0D // Set Tx prescaler bias

SPIWrite 23D,00 // Clear Half VCO cal clock setting

SPIWrite 27D,00 // Clear Half VCO cal clock setting

 

 

SPIWrite 015,04 // Set Dual Synth mode bit

SPIWrite 014,05 // Set Force ALERT State bit

SPIWrite 013,01 // Set ENSM FDD mode

WAIT 1 // waits 1 ms

 

 

SPIWrite 23D,04 // Start RX CP cal

WAIT_CALDONE RXCP,100 // Wait for CP cal to complete, Max RXCP Cal time: 600.000 (us)(Done when 0x244[7]==1)

                                //此处读取的寄存器值为0xa9

 

 

SPIWrite 27D,04 // Start TX CP cal

WAIT_CALDONE TXCP,100 // Wait for CP cal to complete, Max TXCP Cal time: 600.000 (us)(Done when 0x284[7]==1)

                                //此处读取的寄存器值为0xa9

 

 

 

 

//************************************************************

// FDD RX,TX Synth Frequency: 2400.000000,2400.000000 MHz

//************************************************************

//************************************************************

// Setup Rx Frequency-Dependent Syntheisizer Registers

//************************************************************

SPIWrite 23A,4A // Set VCO Output level[3:0]

SPIWrite 239,C0 // Set Init ALC Value[3:0] and VCO Varactor[3:0]

SPIWrite 242,17 // Set VCO Bias Tcf[1:0] and VCO Bias Ref[2:0]

SPIWrite 238,40 // Set VCO Cal Offset[3:0]

SPIWrite 245,00 // Set VCO Cal Ref Tcf[2:0]

SPIWrite 251,00 // Set VCO Varactor Reference[3:0]

SPIWrite 250,70 // Set VCO Varactor Ref Tcf[2:0] and VCO Varactor Offset[3:0]

SPIWrite 23B,A4 // Set Synth Loop Filter charge pump current (Icp)

SPIWrite 23E,D4 // Set Synth Loop Filter C2 and C1

SPIWrite 23F,DF // Set Synth Loop Filter  R1 and C3

SPIWrite 240,09 // Set Synth Loop Filter R3

 

 

//************************************************************

// Setup Tx Frequency-Dependent Syntheisizer Registers

//************************************************************

SPIWrite 27A,4A // Set VCO Output level[3:0]

SPIWrite 279,C0 // Set Init ALC Value[3:0] and VCO Varactor[3:0]

SPIWrite 282,17 // Set VCO Bias Tcf[1:0] and VCO Bias Ref[2:0]

SPIWrite 278,40 // Set VCO Cal Offset[3:0]

SPIWrite 285,00 // Set VCO Cal Ref Tcf[2:0]

SPIWrite 291,00 // Set VCO Varactor Reference[3:0]

SPIWrite 290,70 // Set VCO Varactor Ref Tcf[2:0] and VCO Varactor Offset[3:0]

SPIWrite 27B,A4 // Set Synth Loop Filter charge pump current (Icp)

SPIWrite 27E,D4 // Set Synth Loop Filter C2 and C1

SPIWrite 27F,DF // Set Synth Loop Filter  R1 and C3

SPIWrite 280,09 // Set Synth Loop Filter R3

 

 

//************************************************************

// Write Rx and Tx Frequency Words

//************************************************************

SPIWrite 233,00 // Write Rx Synth Fractional Freq Word[7:0]

SPIWrite 234,00 // Write Rx Synth Fractional Freq Word[15:8]

SPIWrite 235,00 // Write Rx Synth Fractional Freq Word[22:16]

SPIWrite 232,00 // Write Rx Synth Integer Freq Word[10:8]

SPIWrite 231,3C // Write Rx Synth Integer Freq Word[7:0]

SPIWrite 005,11 // Set LO divider setting

SPIWrite 273,00 // Write Tx Synth Fractional Freq Word[7:0]

SPIWrite 274,00 // Write Tx Synth Fractional Freq Word[15:8]

SPIWrite 275,00 // Write Tx Synth Fractional Freq Word[22:16]

SPIWrite 272,00 // Write Tx Synth Integer Freq Word[10:8]

SPIWrite 271,3C // Write Tx Synth Integer Freq Word[7:0] (starts VCO cal)

SPIWrite 005,11 // Set LO divider setting

SPIRead 247 // Check RX RF PLL lock status (0x247[1]==1 is locked)

SPIRead 287 // Check TX RF PLL lock status (0x287[1]==1 is locked)

結果