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AD7658转换正常,但是没有输出

xiongxiong 在 2016-1-14 詢問的問題
最後回覆由hpkamen於2016-1-17提供

最近在用FPGA配一块AD7658芯片,   并行输出到FPGA。发现输出不读,然后我就用chipscope抓了下信号线,如下:

 

可是,无论我输入是多少,抓出来的数据都是 0111 1111 1111(第一路数据,也就是ad_rd的第一个低电平对应的数据,这个芯片支持六路)。

现在是我把ad_convsta拉高以后,ad_busy跟着拉高,按手册上的说法应该是ad已经进入了转换模式了,ad_busy也正常拉低,可是读出来就是不对,时钟是500KHz。困扰我两天了。

这是手册上的时序图:

这是我的原理图:

这是我的代码:

module ad7658(

                                                        input wire sysclk,

                                                        input wire rst_b,

                                                        input wire sel,                //6路和4路选项     1--6路    0--4路

                                                        input wire ad_busy,

                                                        input wire[11:0] ad_data,

                                                        output reg ad_convsta,

                                                        output reg ad_convstb,

                                                        output reg ad_convstc,

                                                        output wire ad_cs,                //低电平有效

                                                        output reg ad_rd,                //低电平有效

                                                        output reg ad_reset,        //高电平有效

                                                        //6路数据

                                                        output reg[11:0] data1,

                                                        output reg[11:0] data2,

                                                        output reg[11:0] data3,

                                                        output reg[11:0] data4,

                                                        output reg[11:0] data5,

                                                        output reg[11:0] data6

                                                       

    );

 

 

 

reg[3:0] state;

//分频

reg[7:0] div_cnt;

reg ad_clk;

 

always @(posedge sysclk or negedge rst_b)

begin

        if(!rst_b)

                begin

                        div_cnt <= 7'h0;

                        ad_clk  <= 0;

                end

        else if(div_cnt == 7'd49)

                begin

                        div_cnt <= 7'h0;

                        ad_clk <= ~ad_clk;

                end

        else

                begin

                        div_cnt <= div_cnt + 1;

                        ad_clk <= ad_clk;

                end

end

 

 

//ad7658配置

assign ad_cs = 0;

always @(posedge ad_clk or negedge rst_b)

begin

        if(!rst_b)

                begin

                        ad_reset <= 1;

                        data1    <= 12'h000;

                        data2    <= 12'h000;

                        data3    <= 12'h000;

                        data4    <= 12'h000;

                        data5    <= 12'h000;

                        data6    <= 12'h000;

                        state                <= 4'd0;

                end

        else

                case(state)

                        4'd0:

                                        begin

                                                ad_reset   <= 0;

                                                ad_convsta <= 0;

                                                ad_convstb <= 0;

                                                ad_convstc <= 0;

                                                ad_rd                  <= 1;

                                                state             <= 4'd1;

                                        end

                        4'd1:

                                        begin

                                                ad_convsta <= 1;

                                                ad_convstb <= 1;

                                                ad_convstc <= 1;

                                                ad_rd                  <= 1;

                                                state                  <= 4'd2;

                                        end

                        4'd2://开始采样

                                        begin

                                                ad_convsta <= 1;

                                                ad_convstb <= 1;

                                                ad_convstc <= 1;

                                                ad_rd                  <= 1;

                                                if(ad_busy == 0)

                                                        state   <= 4'd3;

                                                else

                                                        state   <= 4'd2;

                                        end

                        4'd3:

                                        begin

                                                ad_convsta <= 1;

                                                ad_convstb <= 1;

                                                ad_convstc <= 1;

                                                ad_rd      <= 0;//50MHz晶振20分频,T=400ns > t9=6ns

                                                data1      <= ad_data;  //第一路

                                                state      <= 4'd4;

                                        end

                        4'd4:

                                        begin

                                                ad_convsta <= 1;

                                                ad_convstb <= 1;

                                                ad_convstc <= 1;

                                                ad_rd      <= 1;

                                                state                  <= 4'd5;

                                        end

                        4'd5:

                                        begin

                                                ad_convsta <= 1;

                                                ad_convstb <= 1;

                                                ad_convstc <= 1;

                                                ad_rd      <= 0;

                                                data2                  <= ad_data;  //第二路

                                                state                  <= 4'd6;

                                        end

                        4'd6:

                                        begin

                                                ad_convsta <= 1;

                                                ad_convstb <= 1;

                                                ad_convstc <= 1;

                                                ad_rd                  <= 1;

                                                state                  <= 4'd7;

                                        end

                        4'd7:

                                        begin

                                                ad_convsta <= 1;

                                                ad_convstb <= 1;

                                                ad_convstc <= 1;

                                                ad_rd      <= 0;

                                                data3                  <= ad_data;  //第三路

                                                state                  <= 4'd8;

                                        end

                        4'd8:

                                        begin

                                                ad_convsta <= 1;

                                                ad_convstb <= 1;

                                                ad_convstc <= 1;

                                                ad_rd                  <= 1;

                                                state                  <= 4'd9;

                                        end

                        4'd9:

                                        begin

                                                ad_convsta <= 1;

                                                ad_convstb <= 1;

                                                ad_convstc <= 1;

                                                ad_rd      <= 0;

                                                data4                  <= ad_data;  //第四路

                                                if(sel == 1)   //共6路

                                                        state        <= 4'd10;

                                                else                                //共4路

                                                        state <= 4'd14;

                                        end

                        4'd10:

                                        begin

                                                ad_convsta <= 1;

                                                ad_convstb <= 1;

                                                ad_convstc <= 1;

                                                ad_rd                  <= 1;

                                                state                  <= 4'd11;

                                        end

                        4'd11:

                                        begin

                                                ad_convsta <= 1;

                                                ad_convstb <= 1;

                                                ad_convstc <= 1;

                                                ad_rd      <= 0;

                                                data5                  <= ad_data;  //第五路

                                                state                  <= 4'd12;

                                        end

                        4'd12:

                                        begin

                                                ad_convsta <= 1;

                                                ad_convstb <= 1;

                                                ad_convstc <= 1;

                                                ad_rd                  <= 1;

                                                state                  <= 4'd13;

                                        end

                        4'd13:

                                        begin

                                                ad_convsta <= 1;

                                                ad_convstb <= 1;

                                                ad_convstc <= 1;

                                                ad_rd      <= 0;

                                                data6                  <= ad_data;  //第六路

                                                state                  <= 4'd14;

                                        end

                        4'd14:

                                        begin

                                                ad_convsta <= 1;

                                                ad_convstb <= 1;

                                                ad_convstc <= 1;

                                                ad_rd                  <= 1;

                                                state                  <= 4'd0;

                                        end

                        default:

                                        begin

                                                ad_convsta <= 0;

                                                ad_convstb <= 0;

                                                ad_convstc <= 0;

                                                ad_rd                  <= 1;

                                        end

                endcase

end

                                       

                                       

                                       

endmodule

 

 

 

求帮忙指正下问题,谢谢~

結果