已回答假定已回答

AD9361配置流程问题

mc516 在 2016-6-2 詢問的問題
最後回覆由mc516於2016-6-2提供

论坛的技术高手:

          小弟最近刚刚入手AD9364开发板,想使用FPGA纯逻辑配置AD9364,目前有一个疑惑,如果我已经有了配置文件,比如之前论坛有人提供的BBS.TXT,不知道配置的流程应该怎样,是不是按照附件的寄存器顺序用SPI接口一直写下去就可以了?(写2000多次)还是有特定的配置顺序?请技术支持或者做过的大神指点迷津,阿米托福!

 

附件部分数据

 

//************************************************************

// AD9361 R2 Auto Generated Initialization Script:  This script was

// generated using the AD9361 Customer software Version 2.1.3

//************************************************************

// Profile: LTE 10 MHz

// REFCLK_IN: 40.000 MHz

 

 

RESET_FPGA

RESET_DUT

 

 

BlockWrite 2,6 // Set ADI FPGA SPI to 20Mhz

SPIWrite 3DF,01 // Required for proper operation

ReadPartNumber

SPIWrite 2A6,0E // Enable Master Bias

SPIWrite 2A8,0E // Set Bandgap Trim

REFCLK_Scale 40.000000,1,2 // Sets local variables in script engine, user can ignore

SPIWrite 292,08 // Set DCXO Coarse Tune[5:0].  Coarse and Fine nominal values used with eval system.  Other nominal values may be needed in a customer system

SPIWrite 293,80 // Set DCXO Fine Tune [12:5]

SPIWrite 294,00 // Set DCXO Fine Tune [4:0]

SPIWrite 2AB,07 // Set RF PLL reflclk scale to REFCLK * 2

SPIWrite 2AC,FF // Set RF PLL reflclk scale to REFCLK * 2

SPIWrite 009,07 // Enable Clocks

WAIT 20 // waits 20 ms

 

 

//************************************************************

// Set BBPLL Frequency: 983.040000

//************************************************************

SPIWrite 045,00 // Set BBPLL reflclk scale to REFCLK /1

SPIWrite 046,03 // Set BBPLL Loop Filter Charge Pump current

SPIWrite 048,E8 // Set BBPLL Loop Filter C1, R1

SPIWrite 049,5B // Set BBPLL Loop Filter R2, C2, C1

SPIWrite 04A,35 // Set BBPLL Loop Filter C3,R2

SPIWrite 04B,E0 // Allow calibration to occur and set cal count to 1024 for max accuracy

SPIWrite 04E,10 // Set calibration clock to REFCLK/4 for more accuracy

SPIWrite 043,29 // BBPLL Freq Word (Fractional[7:0])

SPIWrite 042,5C // BBPLL Freq Word (Fractional[15:8])

SPIWrite 041,12 // BBPLL Freq Word (Fractional[23:16])

SPIWrite 044,18 // BBPLL Freq Word (Integer[7:0])

SPIWrite 03F,05 // Start BBPLL Calibration

SPIWrite 03F,01 // Clear BBPLL start calibration bit

SPIWrite 04C,86 // Increase BBPLL KV and phase margin

SPIWrite 04D,01 // Increase BBPLL KV and phase margin

SPIWrite 04D,05 // Increase BBPLL KV and phase margin

WAIT_CALDONE BBPLL,2000 // Wait for BBPLL to lock, Timeout 2sec, Max BBPLL VCO Cal Time: 345.600 us (Done when 0x05E[7]==1)

 

 

SPIRead 05E // Check BBPLL locked status  (0x05E[7]==1 is locked)

 

 

SPIWrite 002,DE // Setup Tx Digital Filters/ Channels

SPIWrite 003,DE // Setup Rx Digital Filters/ Channels

SPIWrite 004,03 // Select Rx input pin(A,B,C)/ Tx out pin (A,B)

SPIWrite 00A,02 // Set BBPLL post divide rate

 

 

//************************************************************

// Program Tx FIR: C:\Program Files\Analog Devices\AD9361R2

// Evaluation Software 2.1.3\DigitalFilters\LTE10_MHz.ftr

//************************************************************

SPIWrite 065,FA // Enable clock to Tx FIR Filter and set Filter gain Setting

SPIWrite 060,00 // Write FIR coefficient address

SPIWrite 061,FB // Write FIR coefficient data[7:0]

SPIWrite 062,FF // Write FIR coefficient data[15:8]

SPIWrite 065,FE // Set Write EN to push data into FIR filter register map

SPIWrite 064,00 // Write to Read only register to delay ~1us

SPIWrite 064,00 // Write to Read only register to delay ~1us

SPIWrite 060,01

SPIWrite 061,00

SPIWrite 062,00

SPIWrite 065,FE

SPIWrite 064,00

SPIWrite 064,00

SPIWrite 060,02

SPIWrite 061,04

SPIWrite 062,00

SPIWrite 065,FE

SPIWrite 064,00

SPIWrite 064,00

SPIWrite 060,03

SPIWrite 061,17

SPIWrite 062,00

SPIWrite 065,FE

SPIWrite 064,00

SPIWrite 064,00

SPIWrite 060,04

SPIWrite 061,24

SPIWrite 062,00

SPIWrite 065,FE

SPIWrite 064,00

SPIWrite 064,00

SPIWrite 060,05

SPIWrite 061,28

SPIWrite 062,00

SPIWrite 065,FE

SPIWrite 064,00

SPIWrite 064,00

SPIWrite 060,06

附件

結果