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高速ADC-AD9239多通道同步问题

wushuang 在 2017-3-24 詢問的問題
最後回覆由hpkamen於2017-3-30提供

     你好,我使用AD9239-210,设计中工作时钟外部信号源输入200MHz,所有8个通道使用同一个时钟源。

板子上两片AD9239,采样后的数据通过GTX接口进入FPGA的内部逻辑。逻辑中数据处理使用的其中一路数据回复出来的随路时钟。

首先,配置AD时用手册上的说明:

     To minimize skew and time misalignment between eachchannel of the digital outputs, the following actions should be taken to ensure that each channel data packet is within ±1 clockcycle of its specified switching time. For some receiver logic,this is not required.

1. Full power-down through external PDWN pin.

2. Chip reset via external RESET pin.

3. Power back up by releasing external PDWN pin

用GTX接受测试数据CCAA DDBB 3553 66A5,使用其内部的COMMA ALIGN(字节对齐)功能,并且一旦对齐到字节CCAA就取消字节对齐功能。发现用ChipScope观察到的八个通道的数据之间会有很大的SKEW,并且每次上电后结果都不一样,有时可以完全对齐,有时八个通道之间有很大差别。

     当八个通道各自都对齐到测试模版时(不管八个通道之间的SKEW),按照手册上描述准备输出采样数据。

1. Initialize a soft reset via Bit 5 of Register 0 (see Table 15).

2. All PGMx pins are automatically initialized as sync pins by default. These pins can be used to lock the FPGA timingand data capture during initial startup. These pins arerespective to each channel (PGM3 = Channel A).

3. Each sync pin is held low until its respective PGMx pinreceives a high signal input from the receiver, during which

time the ADC outputs a training pattern.

4. The training pattern defaults to the values implemented by the user in Register 19 through Register 20.

5. When the receiver finds the frame boundary, the sync identification is deasserted high via the sync pin or via a SPI write. The ADC outputs the valid data on the next packet boundary. The time necessary for sync establishment is highly dependent on the receiver logic processing. Refer to theSwitching Specifications section; the switching timing is

directly related to the ADC channel.

每个通道检测测试模版66A5时,该通道的PGM变为高电平。

 

问题是:我应该采用什么方法把八个通道采样的数据同步到一起,当PGM引脚使能的瞬间,ADC输出完66A5后如果采样数据有延迟,这个延迟大概

結果