I have a project use 2 ad9690 independent,it use the same clock and sysref for test.I have do the follow Experiment：
1.set the 0x200=0x00,0x201=0x01,0x550=0x0f,so it output ramp,i capture the first data use ila when jesd linked,and i found it equals
2.set the 0x200=0x02,0x201=0x01,0x550=0x00,0x310=0x33,0x330=0x33,0x314=0x02,0x334=0x02,so it output sin wave.i capture the first data use ila,when jesd linked,and i found it equals
3.set the 0x200=0x02,0x201=0x01,0x550=0x00,0x310=0x03,0x330=0x03,0x314=0x02,0x334=0x02,so it output the real siganal ,i capture the first data use ila,when jesd linked,and i found it not equals
for example device A analog data is 7 clock ahead of device B,and it stable until power off.when next power on,the diffence changed,for example device A analog datais 11 clock ahead of device B,i want it stable every power on,what can i do with it?