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BF 537 cache configuration

marklmh 在 2013-2-9 詢問的問題
最後回覆由ADI_XUN於2013-2-21提供

Hi,

 

I have one question regarding the cache and memory configuration,

 

Here is what I have in the project options for the cache and memory protection.

cache_memory_protection.jpg

1. What does cache mapping set size mean?

 

 

And here is what I have for the memory map

MEMORY

{

/*

** ADSP-BF537 MEMORY MAP.

**

** The known memory spaces are as follows:

**

** 0xFFE00000 - 0xFFFFFFFF  Core MMR registers (2MB)

** 0xFFC00000 - 0xFFDFFFFF  System MMR registers (2MB)

** 0xFFB01000 - 0xFFBFFFFF  Reserved

** 0xFFB00000 - 0xFFB00FFF  Scratch SRAM (4K)

** 0xFFA14000 - 0xFFAFFFFF  Reserved

** 0xFFA10000 - 0XFFA13FFF  Code SRAM/CACHE (16K)

** 0xFFA0C000 - 0xFFA0FFFF  Reserved

** 0xFFA08000 - 0xFFA0BFFF  Instruction Bank B SRAM (16K)

** 0xFFA00000 - 0xFFA07FFF  Instruction Bank A SRAM (32K)

** 0xFF908000 - 0xFF9FFFFF  Reserved

** 0xFF904000 - 0xFF907FFF  Data Bank B SRAM/CACHE (16K)

** 0xFF900000 - 0XFF903FFF  Data Bank B SRAM (16K)

** 0xFF808000 - 0xFF8FFFFF  Reserved

** 0xFF804000 - 0xFF807FFF  Data Bank A SRAM/CACHE (16K)

** 0xFF800000 - 0XFF803FFF  Data Bank A SRAM (16K)

** 0xEF000800 - 0xFF800000  Reserved

** 0xEF000000 - 0xFF8007FF  Boot ROM (2K)

** 0x20400000 - 0xEEFFFFFF  Reserved

** 0x20300000 - 0x203FFFFF  ASYNC MEMORY BANK 3 (1MB)

** 0x20200000 - 0x202FFFFF  ASYNC MEMORY BANK 2 (1MB)

** 0x20100000 - 0x201FFFFF  ASYNC MEMORY BANK 1 (1MB)

** 0x20000000 - 0x200FFFFF  ASYNC MEMORY BANK 0 (1MB)

** 0x00000000 - 0x08000000  SDRAM MEMORY (16MB - 128MB)

**

** Notes:

** 0xFF807FEF-0xFF807FFF

**   Required by boot-loader. Used as heap or cache below which is ok. Cannot

**   contain initialized data or code.

*/

 

 

   MEM_L1_SCRATCH          { TYPE(RAM) START(0xFFB00000) END(0xFFB00FFF) WIDTH(8) }

   MEM_L1_CODE_CACHE       { TYPE(RAM) START(0xFFA10000) END(0xFFA13FFF) WIDTH(8) }

   MEM_L1_CODE             { TYPE(RAM) START(0xFFA00000) END(0xFFA0BFFF) WIDTH(8) }

   MEM_L1_DATA_B_CACHE     { TYPE(RAM) START(0xFF904000) END(0xFF907FFF) WIDTH(8) }

   MEM_L1_DATA_B           { TYPE(RAM) START(0xFF900000) END(0xFF903FFF) WIDTH(8) }

   MEM_L1_DATA_A_CACHE     { TYPE(RAM) START(0xFF804000) END(0xFF807FFF) WIDTH(8) }

   MEM_L1_DATA_A           { TYPE(RAM) START(0xFF800000) END(0xFF803FFF) WIDTH(8) }

   MEM_ASYNC3              { TYPE(ASYNC3_MEMTYPE) START(0x20300000) END(0x203FFFFF) WIDTH(8) }

   MEM_ASYNC2              { TYPE(ASYNC2_MEMTYPE) START(0x20200000) END(0x202FFFFF) WIDTH(8) }

   MEM_ASYNC1              { TYPE(ASYNC1_MEMTYPE) START(0x20100000) END(0x201FFFFF) WIDTH(8) }

   MEM_ASYNC0              { TYPE(ASYNC0_MEMTYPE) START(0x20000000) END(0x200FFFFF) WIDTH(8) }

   MEM_SDRAM0_BANK0        { TYPE(RAM) START(0x00000004) END(0x00ffffff) WIDTH(8) }

   MEM_SDRAM0_BANK1        { TYPE(RAM) START(0x01000000) END(0x01ffffff) WIDTH(8) }

   MEM_SDRAM0_BANK2        { TYPE(RAM) START(0x02000000) END(0x02ffffff) WIDTH(8) }

   MEM_SDRAM0_BANK3        { TYPE(RAM) START(0x03000000) END(0x03ffffff) WIDTH(8) }

 

   /*$VDSG<insert-new-memory-segments>                          */

   /* Text inserted between these $VDSG comments will be preserved */

   /*$VDSG<insert-new-memory-segments>                          */

 

} /* MEMORY */

 

2. It has 64MB SDRAM, in the above configuration, which part of SDRAM(memory arrange) are cached and which part are not.

 

3. Can I configure all the SDRAM as cacheable SDRAM, or configure specified memory arrange of SDRAM are cacheable SDRAM?

結果