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AD9789 issue for DTMB

Seven.Wang 在 2018-7-16 詢問的問題

Hi All:

客户在使用AD9789设计DTMB时遇到一些问题,请参考。

1AD9789的应用硬件拓扑,主要用AD9789来实现上变频功能

   001.jpg

 

2、接口形式:

    2.1FPGAAD9789通过LVDS物理接口通信,LVDS的信号带宽为16bit,采用DDR模式传输

           所以FPGAAD9789之间的数据带宽是32bit

    2.2AD9789的差分经过如下耦合网络将射频信号输出到F母头

        

  3、总体现象描述——AD9789工作在Channelizer mode ”FPGA输出的调制数据通过LVDS接口送给AD9789

       AD9789送出的RF信号送给 DTMB的接收机(高频头+解调)。 但接收机的解调模块无法解调出正确的数据。

 

 

4、原因分析—— 问题可能出在四个环节,分别是1FPGA调制模块异常(全数字);2FPGAAD9789之间的数据传输异常;3AD9789

           的使用异常;4AD9789输出射频电路设计导致的射频信号异常。现在有以下几个问题跟AD9789有相关,请帮忙确认:

002.jpg003.jpg004.jpg

 

 

    4.1FPGA依据AD9789输出的DCO_P/N(时钟),FS_P/N(符号同步),通过DDR模式送出LVDS差分数据,存在AD9789接收异常的可能

    问题1 AD9789LVDS接收端口为了正确地接收数据,需要配置LAT(reg0x21[2:0])DSC(reg0x23[7:4])SNC(reg0x23[3:0]) 三个参数,

如何检验确认这三个参数配置是否正常?

 

    4.2AD9789的配置不当也可能会导致射频信号不能被正常接收解调,相关寄存器配置参数如下所示。

     问题2 帮忙确认A9789的寄存器配置是否正确,帮忙确认配置顺序是否正确。

 

Write_AD9789_Single(0x32,0x9E);//Enable the clock receiver and set the clock CML
Write_AD9789_Single(0x31,0x10);//0x31 adapt its default value 0xF0
Write_AD9789_Single(0x30,0x80);//Enable duty cycle correction

//Enable digital clocks
Write_AD9789_Single(0x24,0x00);//
Write_AD9789_Single(0x24,0x80);//


//Set up mu controller
Write_AD9789_Single(0x2F,0xCE);//
Write_AD9789_Single(0x33,0x42);//
Write_AD9789_Single(0x39,0x4E);//
Write_AD9789_Single(0x3A,0x6C);//

Write_AD9789_Single(0x03,0x00);//Disable all interrupts
Write_AD9789_Single(0x04,0xFE);//Clear all interrupts
Write_AD9789_Single(0x03,0x0C);//Enable mu control interrupts
Write_AD9789_Single(0x33,0x43);//Enable mu delay controller

//Set up digital datapath base register
Write_AD9789_Single(0x06,0xD0);//bypass filter4
0xD0
Write_AD9789_Single(0x08,0x10);//0.25 SUMSCALE for 4 channel, 1.0 for one channel
Write_AD9789_Single(0x09,0x20);//1.0 INSCALE

//NCO0
Write_AD9789_Single(0x0A,0x36);// 62M
Write_AD9789_Single(0x0B,0xD0);//
Write_AD9789_Single(0x0C,0x69);//
//NC1
Write_AD9789_Single(0x0D,0x77);//70M
Write_AD9789_Single(0x0E,0x77);//
Write_AD9789_Single(0x0F,0x77);//
//NC2
Write_AD9789_Single(0x10,0xB8);//78M
Write_AD9789_Single(0x11,0x1E);//
Write_AD9789_Single(0x12,0x85);//
//NC3
Write_AD9789_Single(0x13,0xF9);//86M
Write_AD9789_Single(0x14,0xC5);//
Write_AD9789_Single(0x15,0x92);//

//Set up rate converter
Write_AD9789_Single(0x16,0x00);//
Write_AD9789_Single(0x17,0x00);//
Write_AD9789_Single(0x18,0xFC);//Q

Write_AD9789_Single(0x19,0x00);//
Write_AD9789_Single(0x1A,0x40);//
Write_AD9789_Single(0x1B,0x9C);//P

//Set up BPF center frequency,
Write_AD9789_Single(0x1C,0xE4);// 824M
Write_AD9789_Single(0x1D,0x57);//

//Set up interface

//very important value for data capture
Write_AD9789_Single(0x20,0x05);//
Write_AD9789_Single(0x21,0x7A);//   LTNCY[2:0] need check?
Write_AD9789_Single(0x22,0x1F);//   dco frequency 2400/16*1 = 150M
Write_AD9789_Single(0x23,0x14);//   Internal Clock Phase Adjust Register,need check

//Set up channel gains
Write_AD9789_Single(0x25,0x80);// gain is 1.0
Write_AD9789_Single(0x26,0x80);//
Write_AD9789_Single(0x27,0x80);//
Write_AD9789_Single(0x28,0x80);//

//Set up spectral invert
Write_AD9789_Single(0x29,0x00);//
spectrally noninvert
have not understand

//Set up full-scale current
Write_AD9789_Single(0x3C,0xD0);// ~25mA
Write_AD9789_Single(0x3D,0x02);//

do {
//Wait until mu delay controller is locked (SPI read),min75us
Delay(20000);//1ms
ReadAD9789Data = Read_AD9789_Single(0x04);
}
while((ReadAD9789Data&0x08)!=0x08);
//read the 0x04 to check the LOCKACQ is 1

Write_AD9789_Single(0x1E,0x80);  //Update rate converter and BPF


//Update interface clocks
Write_AD9789_Single(0x24,0x00);//generate the transition from 0 to 1
Write_AD9789_Single(0x24,0x80);//

Write_AD9789_Single(0x05,0x0F);
//Enable channels,0x01-0x0F
Write_AD9789_Single(0x03,0x8E);
//Enable other interrupts if desired




  1. 4.3、对AD9789输出的射频信号处理变换网络,我们参考如下图进行的设计

问题3:这个网络是否需要优化改进,这部分变换网络是否会导致接收端异常的可能?

            如果会,影响的因素是什么?

 

问题4:对于AD9789输出的射频信号,我们如何判断射频信号的质量是否符合我们要求?

          分别借助哪些仪器?

 

以上问题,请帮忙协助解决,谢谢!

結果