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ADUC7021 pll问题

peter_yang 在 2013-11-19 詢問的問題
最後回覆由ADI_XUN於2013-11-26提供

大家好,aduc7021英文手册里谈到时钟从内部晶振切换到外部晶振时有这样一段话(大概在第51页):

External Crystal Selection

To switch to external crystal, clear the OSEL bit in the PLLCON MMR (see Table 32). In noisy environments, noise might couple to the external crystal pins and PLL could lose lock momentarily. A PLL interrupt is provided in the interrupt controller. The core clock is halted immediately and this interrupt is only serviced once the lock has been restored.

In case of crystal loss, the watchdog timer should be used.During initialization, a test on the RSTSTA can determine if the reset came from the watchdog timer.

我想请教的是:上面第二段话里的watchdog timer指的是内部的还是外部的?具体的防止crystal loss的过程是怎样的?谢谢!

結果